1. Field of the Invention
The present invention relates to semiconductor structures and methods of forming semiconductor structures, and more particularly to gate dielectric layers and methods of fabricating gate dielectric layers.
2. Description of the Related Art
With advances associated with electronic products, semiconductor technology, has been widely applied in manufacturing memories, central processing units (CPUs), liquid crystal displays (LCDs), light emission diodes (LEDs); laser diodes and other devices or chip sets. In order to achieve high integration and speed targets, dimensions of semiconductor integrated circuits, such as gate dielectric layers, continue shrinking and various materials, such as high-k dielectric materials, have been used along with techniques for overcoming manufacturing obstacles associated with these materials.
FIG. 1 is a cross-sectional view of a prior art high-k gate dielectric layer formed over a substrate. A high-k gate dielectric layer 110 is formed over a substrate 100. The high-k gate dielectric layer 110 includes ions, such as nitrogen (N), hafnium (Hf) or zirconium (Zr), which increases the dielectric constant of the high-k gate dielectric layer 110. For example, a dielectric constant of a gate oxide layer is about 3.9 and a dielectric constant of an HfO2 layer is about 22. A high-k dielectric layer having a high physical thickness provides a desired equivalent oxide thickness (EOT) to that provided by an oxide layer having a low physical thickness. An oxide layer having a physical thickness of about 15 Å provides an EOT of about 15 Å. An HfO2 layer providing an EOT of about 15 Å, however, may have a physical thickness of about 85 Å. The HfO2 layer having an 85-Å physical thickness can tolerate a high gate voltage applied thereto. Accordingly, a transistor having an HfO2 layer as a gate dielectric layer not only provides the same electrical performance as a transistor having a 15-Å oxide layer, but also has a current leakage lower than the transistor having the oxide dielectric layer.
By way of background, U.S. Pat. No. 6,268,269 provides a description of a process for reducing interface-trapped charges, the entirety of which is hereby incorporated by reference herein. U.S. Pat. No. 4,140,548 provides a description of a process for manufacturing metal-oxide-semiconductor (MOS) devices, the entirety of which is also hereby incorporated by reference herein.
From the foregoing, improved gate dielectric layers and methods of forming gate dielectric layers are desired.